Jianping Zeng

PhD Student

Lawson Hall 3133-6, 305 N. University Street West Lafayette, IN 47907
Department of Computer Science
Purdue University
Email: zeng207 (at) purdue (dot) edu

Google Scholar DBLP

Biography

I am a final-year PhD candidate advised by Prof. Changhee Jung in the department of Computer Science at Purdue University. In the meanwhile, I also closely work with Prof. Dongyoon Lee at Stony Brook University, Prof. Trevor E. Carlson at National University of Singapore, and Prof. Jongouk Choi at University of Central Florida. Prior to joining Purdue University, I worked as a compiler engineer with focuses on optimizing the middle-end and backend of GCC (GNU Compiler Collection) for CSKY architecture (an embedded architecture widely used in network switch, printer, etc) of Alibaba T-Head Semiconductor. I obtained my Master degree from School of Computer Science of Huazhong University of Science and Technology (HUST), China.


I am looking for a tenure-track assistant professor position for the upcoming 2024 hiring cycle. Please feel free to contact me if my research fits your department!


Research

My research interests generally lie in designing more reliable and performant computing systems including server-class systems and energy-harvesting systems against soft errors and power failures. To achieve that, I usually codesign compiler and architecture to maintain a minimal hardware complexity while achieving high performance. My research works are usually published at top-tier system venues, e.g., PLDI, MICRO, HPDC, ISCA, and RTSS.

News

  • July 2023: RTailor accepted to RTSS 2023!
  • July 2023: PPA and SweepCache accepted to MICRO 2023!
  • March 2023: WL-Cache accepted to ISCA 2023. Thanks a lot to my collaborators!
  • March 2023: I will join Memory Solutions Lab (MSL) of Samsung Semiconductor, Inc as a System Architecture Intern this summer.
  • Feb 2023: One paper accepted to NVMW 2023.
  • April 2022: One paper accepted to NVMW 2022.
  • March 2022: One paper accepted to HPDC 2022.
  • March 2022: I will join the Computing Technology Lab of Alibaba Group, US this summer as a Research Intern focusing on computer architecture.
  • July 2021: Two papers (ReplayCache and Turnpike) accepted to MICRO 2021.
  • February 2020: One paper (Penny) accepted to PLDI 2020.

    • Publications

    Conference Papers

  • [TOP-TIER] RTailor: Parameterizing Soft Error Resilience for Mixed-Criticality Real-Time Systems [PDF]
    Shao-Yu Huang, Jianping Zeng, Xuanliang Deng, Sen Wang, Ashrarul Haq Sifat, Burhanuddin Bharmal, Jia-Bin Huang, Ryan Williams, Haibo Zeng and Changhee Jung
    44th International IEEE Real-Time Systems Symposium, Taipei, December 2023.

  • [TOP-TIER] Persistent Processor Architecture [PDF] [PPT]
    Jianping Zeng, Jungi Jeong, Changhee Jung
    56th International IEEE/ACM Symposium on Microarchitecture (MICRO-2023), Toronto, Canada, October 2023.
    Acceptance rate: 23.8% (101 out of 404 submissions)

  • [TOP-TIER] SweepCache: Intermittence-Aware Cache on the Cheap [PDF] [PPT]
    Yuchen Zhou, Jianping Zeng, Jungi Jeong, Jongouk Choi, Changhee Jung
    56th International IEEE/ACM Symposium on Microarchitecture (MICRO-2023), Toronto, Canada, October 2023.
    Acceptance rate: 23.8% (101 out of 404 submissions)

  • [TOP-TIER] Write-Light Cache for Energy Harvesting Systems [PDF]
    Jongouk Choi, Jianping Zeng, Dongyoon Lee, Changwoo Min, Changhee Jung
    50th International ACM/IEEE Symposium on Computer Architecture (ISCA-2023), Orlando, USA, June 2023.
    Acceptance rate: 21% (79 out of 373 submissions)

  • [TOP-TIER] Capri: Compiler and Architecture Support for Whole-System Persistence [PDF] [PPT]
    Jungi Jeong, Jianping Zeng, Changhee Jung
    31th International ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC-2022), Minneapolis, USA, June 2022.
    Acceptance rate: 19% (21 out of 108 submissions)

  • [TOP-TIER] ReplayCache: Enabling Volatile Caches for Energy Harvesting Systems [PDF] [PPT]
    Jianping Zeng, Jongouk Choi, Xinwei Fu, Ajay P. Shreepathi, Dongyoon Lee, Changwoo Min, and Changhee Jung
    54th IEEE/ACM International Symposium on Microarchitecture (MICRO-2021), Online, October 2021.
    Acceptance rate: 21.8% (94 out of 430 submissions)

  • [TOP-TIER] Turnpike: Lightweight Soft Error Resilience for In-Order Cores [PDF] [PPT]
    Jianping Zeng, Hongjune Kim, Jaejin Lee, and Changhee Jung
    54th IEEE/ACM International Symposium on Microarchitecture (MICRO-2021), Online, October 2021.
    Acceptance rate: 21.8% (94 out of 430 submissions)

  • [TOP-TIER] Compiler-Directed Soft Error Resilience for Lightweight GPU Register File Protection [PDF]
    Hongjune Kim, Jianping Zeng, Qingrui Liu, Mohammad Abdel-Majeed, Jaejin Lee, and Changhee Jung
    41th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI-2020), Online, June 2020.
    Acceptance rate: 22.5% (77 out of 341 submissions)


    • Workshop Papers

  • Capri: Compiler and Architecture Support for Whole-System Persistence [PDF]
    Jungi Jeong, Jianping Zeng, Changhee Jung
    14th Non-Volatile Memories Workshop (NVMW), San Diego, USA, March 2023.

  • ReplayCache: Enabling Volatile Caches for Energy Harvesting Systems [PDF]
    Jianping Zeng, Jongouk Choi, Xinwei Fu, Ajay P. Shreepathi, Dongyoon Lee, Changwoo Min, and Changhee Jung
    13th Non-Volatile Memories Workshop (NVMW), San Diego, USA, May 2022.

    • Working Experiences

  • Research Intern: May 2023-August 2023, Samsung Memory Solutions Lab (MSL) managed by Dr. Yang Seok Ki.
    I interned at Samsung MSL to design a more energy-efficiency ECC DRAM without losing its reliability.
  • Research Intern: May 2022-August 2022, Alibaba DAMO Academy, Computing Technology Lab directed by Prof. Yuan Xie.
    I worked on optimizing the ARM memory fence instructions, which is particular of importance for the server cores scaling up to 256 cores. This is because ARM processor is now prevalent in server fleets due to its energy-efficiency and low license cost. However, the memory fences, highly affecting the performance of multi-threaded applications, on ARM cores are not optimized in contemporary ARM server processors.
  • Senior Compiler Engineer: Dec 2017-July 2018, Alibaba T-Head Semiconductor.
    After obtaining my Master degree from HUST, I worked at Alibaba T-Head as a senior compiler engineer with the focus on analyzing and uncovering the performance bottleneck of GCC for CSKY architecture in terms of run-time performance and code size. What I did is fixing a series of performance bugs of GCC for CSKY in GCC's local register allocation and its naive instruction selector though there is a post-isel phase to combine multiple simple instructions into a more sophisticated form.
  • Senior Software Engineer: June 2017-Dec 2017, Alibaba Taobao BU.
    I worked there to design a static analyzer for C/C++/Objective-C/Objective-C++ based on Clang, which is widely used for statically validating the correctness and ensuring the robustness of Taobao App (the most popular online shopping application in China).
  • Software Engineer Intern: June 2016-August 2016, Alibaba Group.
    During the summer 2016, I interned at Alibaba Group to develop a prototype (so-called StaticJS) that optimizes the performance of Google V8 JavaScript Virtual Machine. That is, StaticJS annotates program variables with type information and then passes the type information to the middle-end optimizations and code generation. As such, StaticJS avoids the drawbacks of dynamic typing in JavaScript to some extent and achieves higher performance transparently.

    • Services

  • Organization Committee
      Languages, Compilers, Tools and Theory of Embedded Systems (LCTES): 2020 (Web Chair).
  • Journal Reviewer
      Computer Architecture Letter (CAL): 2022.
  • Sub-reviewer
      Architectural Support for Programming Languages and Operating Systems (ASPLOS): 2020, 2022-2023.
      USENIX Annual Technical Conference (ATC): 2020.
      International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES): 2020, 2023.
      International Conference on Compiler Construction (CC): 2020.
      International Symposium on Computer Architecture (ISCA): 2023.
      Principles and Practice of Parallel Programming (PPoPP): 2020-2023.
      International Symposium on Microarchitecture (MICRO): 2020, 2022.
      International Symposium on High-Performance Parallel and Distributed Computing (HPDC): 2020, 2022.
      International Symposium on Code Generation and Optimization (CGO): 2020, 2022.

    • Achievements

  • NVMW Travel Award: 2022, 2023.

    • Teaching Experience

  • CS 352 Guest Lecture (Purdue University): Compilers: Principles and Practice (Fall 2023)

    • Software Packages
    BarGraphGenerator: an easy-to-use bar graph generator.

    I have developed a bar graph generator written in Python 3 by leveraging Matplotlib. With input plain text file provided, it generates various bar graphs, e.g., simple bar graph, cluster graph, stacked graph, and stacked cluster graph with option specified in the input file. Please see the example files under the examples directory. All of these bar graphs in my published papers are plotted by this tool!

    This project was inspired by Derek Bruening's bargraph tool. However, this tool is dependent on GNU libraries which have some compatible issues with MacOS and modern Linux distributions. More importantly, his tool is written in perl which is not friendly to use and maintain in my end.

    I try to response to these inquiries about how to use my tool in a best effort manner but can not promise that. Obviously, bug fix and patching requrests are welcome!

    For Fun

    When I was a graduate student at HUST, I have been developing a research compiler, XCC written in Java for fun and learning purpose. This compiler accepts the LLVM-3 compatible bitcode as an input and generates assembly code for x86 and ARMv7 ISA. XCC can work together with dragonegg-3.0 and LLVM 3.0 to generate binaries for SPEC CPU2006 programs. Notably, LLVM 3.0 just provides some interfaces to dragonegg for translating C/C++ source code into LLVM IR which is fed back to XCC to generate assembly code.