TRANSACT 2011 – Final Program

Sunday, June 5

 

Breakfast: 8-8:45

Session 1: Hardware
8:45-10:10

Chair: Jaewoong Chung, Intel

From Lightweight Hardware Transactional Memory to Lightweight Lock Elision

Martin Pohlack and Stephan Diestelhorst (AMD)

Presentation slides

TSO-Atomicity: Efficient TSO Enforcement for Optimization

Cheng Wang, Youfeng Wu and Jaewoong Chung (Intel Corporation)

Presentation slides

A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory

Ege Akpinar, Saša Tomić, Osman Unsal, Adrián Cristal and Mateo Valero (Barcelona Supercomputing Center)

Presentation slides

Break 10:10-10:30

Session 2: Conflicts and Contention
10:30-11:20

Chair: Ravi Rajwar, Intel

The Universal Transactional Memory Construction

Jons-Tobias Wamhoff and Christof Fetzer (Dresden University of Technology and TU Dresden)

Presentation slides

Toxic Transactions

Yujie Liu and Michael Spear (Lehigh University)

Session 3: Semantics
11:20-12:20

Chair: Mike Swift, University of Wisconsin

Region-Based Dynamic Separation for STM Haskell

Laura Effinger-Dean and Dan Grossman (University of Washington)

Presentation slides

Transaction Correctness for Secure Nested Transactions

Dominic Duggan and Ye Wu (Stevens Institute of Technology)

Lunch: 12:20-1:45

Session 4: Run-time systems
1:45-3:30

Chair: Chris Rossbach, Microsoft Research

Collecting Transactional Garbage

Fadi Meawad, Ryan Macnak and Jan Vitek (Purdue University)

Presentation slides

Towards Applying Machine-Learning to Adaptive Transactional Memory

Qingping Wang, Sameer Kulkarni, John Cavazos and Michael Spear (Lehigh University and University of Delaware)

Revisiting Condition Variables and Transactions

Victor Luchangco and Virendra J. Marathe (Oracle Labs)

Presentation slides

Break: 3:30-3:50

Session 5: STM Implementation
3:50-5:30

Chair: Michael Spear, Lehigh University

Supporting STM in Distributed Systems: Mechanisms and a Java Framework

Mohamed M. Saad and Binoy Ravindran (Virginia Tech)

Presentation slides

HParSTM: A Hierarchy-based STM Protocol for Supporting Nested Parallelism

Ranjeet Kumar and Krishnamurthy Vidyasankar (Memorial University of Newfoundland)

Interchangeable Back Ends for STM Compilers

Gokcen Kestor, Luke Dalessandro, Adrián Cristal, Michael L. Scott and Osman Unsal (IIIA - Artificial Intelligence Research Institute CSIC - Spanish National Research Council, Universitat PolitŹcnica de Catalunya, Barcelona Supercomputing Center, and University of Rochester)

Presentation slides

Discussion: 5:00-5:30

End of workshop: 5:30