/************************************************************************/
/*									*/
/* Configuration - Xinu device configuration specification file		*/
/*									*/
/* This file becomes input to the config program, which generates	*/
/* 		conf.h  and  conf.c					*/
/*									*/
/* Entries for a device specify the functions that handle each of the	*/
/* high-level I/O operations as follows:				*/
/*									*/
/*	-i    init	-o    open	-c    close			*/
/*	-r    read	-w    write	-s    seek			*/
/*	-g    getc	-p    putc	-n    control			*/
/*	-intr int_hndlr	-csr  csr	-irq  irq			*/
/*									*/
/************************************************************************/

/* Type Declarations for both real- and pseudo- device types */

/* type of a null device */
null:
	on nothing
		-i ionull	-o ionull	-c ionull
		-r ionull	-g ionull	-p ionull
		-w ionull	-s ioerr

/* type of a tty device */
tty:
	on uart
		-i ttyinit      -o ionull       -c ionull
		-r ttyread      -g ttygetc      -p ttyputc
		-w ttywrite     -s ioerr        -n ttycontrol
		-intr ttydispatch

/* type of a ethernet device */
eth:
	on quark_eth
		-i ethinit	-o ioerr	-c ioerr
		-r ethread	-g ioerr	-p ioerr
		-w ethwrite	-s ioerr	-n ethcontrol
		-intr ethdispatch

/* type of namespace device */
nam:
	on top
		-i naminit 	-o namopen 	-c ioerr
		-r ioerr 	-g ioerr 	-p ioerr
		-w ioerr 	-s ioerr 	-n ioerr
		-intr ioerr

%%

/* Actual device declarations that each give the name of a device that	*/
/*   will be present in the system					*/

   /* Define the console device to be a tty and specify CSR*/
   CONSOLE is tty  on uart  csr 0001770 -irq 0052

   /* Define a null device */
   NULLDEV is null on nothing

   /* Physical Ethernet (raw packet transfer) */
   ETHER0 is eth   on quark_eth csr 0 -irq 0053

   /* Define a namespace device */
   NAMESPACE is nam on top

%%

/* Configuration and Size Constants */

#define	NPROC	     100	/* number of user processes		*/
#define	NSEM	     100	/* number of semaphores			*/
#define	IRQBASE	     32		/* base ivec for IRQ0			*/
#define	IRQ_TIMER    IRQ_HW5	/* timer IRQ is wired to hardware 5	*/
#define	IRQ_ATH_MISC IRQ_HW4	/* Misc. IRQ is wired to hardware 4	*/
#define CLKFREQ      200000000	/* 200 MHz clock			*/
