Project Summary

One of the applications that is addressed by logic analyzer measurement instruments are engineers who are responsible for testing and characterizing new digital IC designs. Many of these customers would like to be able to create “expected results” files (or reference memories) for their TLA logic analyzer from their logic simulator to validate the product from their design. Tektronix had this capability for a previous logic analyzer, but it is outdated and not supported in the current product.

The goal of this project is to product a conversion package that would translate the output of one or more simulator output formats to a generic format that can then be converted into a TLA 700 reference memory file to be used to compare against data acquired by the logic analyzer.

Requirements

A system exists today with the following features:

CAD vendors produce various formats, that describe “event” data for each individual pin in the system, e.g. when a pin changes value and at what time instance. Translators would then convert that data into a standard (at the time) Tektronix format. The next stage would then “sample” the data (which is software equivalent of what the logic analyzer does) on a fixed time interval for a specific pin and dump only those values the customer is interested in (from a “Map file”) into another standard (at the time) Tektronix format. This data could then be formed into a reference memory file by the next stage and then sent to the logic analyzer for use in comparing expected values with real values being acquired by the logic analyzer from the user’s actual hardware. This would be similar to a software simulator that would output data that the engineer could compare with the actual running results.

The goal of this project is to bring the toolset up to today’s standards with CAD vendor’s output file formats and target the newer Tektronix TLA 700 logic analyzer family. These formats would have to be researched for the most appropriate one to translate, and then a decision would need to be made about what intermediate format is best. It may be possible to give access to certain Tektronix field personnel to gather specific customer requirements. Additional decisions can be made by the team as to the appropriate number of steps in the process and the specific tools to be used. The final product does, however, need to run on a Windows® platform. A bonus would be if the application would run on multiple platforms (e.g. Unix, etc.), especially where the CAD vendors are prevalent.

Initially, we would target Verilog, but Mentor would also be desired, depending on the Tektronix field personnel..

Because there is specific information about the TLA reference memory needed to create a reference memory, the proposal is that Tektronix will modify an existing tool for the project use.

This project will require access to a TLA logic analyzer and access to vendor files for a known device. These either already exist at Purdue or will be provided to the project. It would be very useful if there were an opportunity to utilize other Purdue EE projects.

Purdue will provide the PC’s running Windows® 98/NT and all software tools.

Benefit to Tektronix

We would intend on giving this tool to our customers to utilize logic analyzers in their actual design process. This would both enhance the usage of the instrument aid the customers in the debug of their designs.. Ultimately, it could lead to more sales of instruments.