Preliminary programme now available


Register Online


Call for Participation

MSPC 2006 focuses on improving the memory system performance and correctness of general-purpose programs. MSPC continues the successful series of MSP workshops held in 2002 (Berlin), 2004 (Washington, DC), and 2005 (Chicago). This multi-disciplinary workshop fosters collaboration among researchers in a range of fields including compilers, memory management, programming languages, architecture, operating systems, performance evaluation, and database systems. Papers are solicited on all aspects of memory system performance and correctness. Areas of interest include but are not limited to the following topics:

  1. Analysis of memory systems performance (including power, bandwidth, and latency)

  2. Static and dynamic techniques for understanding and improving memory performance

  3. Hardware and software techniques for ensuring memory safety and detecting memory-related bugs (e.g., memory leaks, dangling pointers, out-of-bounds memory accesses, invalid C pointer arithmetic)

  4. Hardware memory models and their impact on software

  5. Specifications of programming language (and library) shared memory semantics

  6. Better shared-memory programming models (e.g., transactional memory)

  7. Data race detection and debugging of programs with (possibly intentional) data races

  8. Managed memory and garbage collection optimizations

  9. Memory hierarchy design for chip multiprocessors (CMPs)

  10. Pre-fetching and compression to improve memory system performance

  11. Code, data, or page placement to eliminate page faults and cache misses

  12. Memory system issues in embedded computers and tiny devices

  13. Impact of new storage technologies

Software, hardware, and hybrid approaches are encouraged.  In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.

Important Dates


Abstract submission:

Monday, July 24, 2006

Paper submission (firm deadline):

Friday July 28, 2006

11:59:59 pm EDT

Notification:

September 8, 2006

Final submission:

September 22, 2006

Organization


Steering Committee

Steve Blackburn, Intelhttp://cs.anu.edu.au/~Steve.Blackburn/

Trishul Chilimbi, Microsofthttp://research.microsoft.com/~trishulc/

Chen Ding, U Rochesterhttp://www.cs.rochester.edu/~cding/

Ben Zorn, Microsofthttp://research.microsoft.com/~zorn/

General Chair

Antony Hosking, Purdue Uhttp://www.cs.purdue.edu/~hosking

Program Chair

Ali-Reza Adl-Tabatabai, Intelmailto:ali-reza.adl-tabatabai@intel.com?subject=MSPC'06

Program Committee

Emery Berger, U Mass, Amhersthttp://www.cs.umass.edu/~emery/

Hans Boehm, HP Labshttp://www.hpl.hp.com/personal/Hans_Boehm

Martin Burtscher, Cornell Uhttp://www.csl.cornell.edu/~burtscher

Barbara Chapman, U Houstonhttp://www.cs.uh.edu/~chapman

David Chase, Sun Microsystems


Brad Chen, Google


Amer Diwan, U Colorado, Boulderhttp://www.cs.colorado.edu/people/amer_diwan.html

Cormac Flanagan, UC Santa Cruzhttp://www.cse.ucsc.edu/~cormac

Thomas Gross, ETH Zürichhttp://www.lst.inf.ethz.ch/people/trg.html

Dan Grossman, U Washingtonhttp://www.cs.washington.edu/homes/djg

Glenn Reinman, UCLAhttp://www.cs.ucla.edu/~reinman

Qing Yi, UT San Antoniohttp://www.cs.utsa.edu/~qingyi


Links



Call for Papers [pdf]

APSLOS XII

ACM SIGPLAN

MSP 2005

MSP 2004

MSP 2002

 
MSPC 2006

Memory Systems Performance and Correctness

ACM SIGPLAN Workshop


October 22, 2006 • San José, California, USA • Co-located with ASPLOS XII