Network Processor Publications

Papers

Overview

• Technologies and building blocks for fast packet forwarding Bux, W.; Denzel, W.E.; Engbersen, T.; Herkersdorf, A.; Luijten, R.P. IEEE Communications Magazine , Volume: 39 Issue: 1 , Jan. 2001 Page(s): 70 -77
• The new chips on the block [network processors] Geppert, L. IEEE Spectrum , Volume: 38 Issue: 1 , Jan. 2001 Page(s): 66 -68
• Hot chips 12 Dally, W.J.; Tremblay, M.; Baum, A.J. IEEE Micro , Volume: 21 Issue: 2 , March-April 2001 Page(s): 13 -15
• A survey of highly integrated Ethernet DataComm devices Hubbs, B. Aerospace Conference, 1998 IEEE , Volume: 4 , 1998 Page(s): 489 -498 vol.4
• Architectures for network, communications, or packet processors On-chip communication architecture for OC-768 network processors; Faraydon Karim, Anh Nguyen, Sujit Dey and Ramesh Rao; Proceedings of the 38th Conference on Design Automation Conference, 2001, Pages 678 - 683
• The iflow address processor O'Connor, M.; Gomez, C.A. IEEE Micro , Volume: 21 Issue: 2 , March-April 2001 Page(s): 16 -23
• Efficient exploration of the SoC communication architecture design space Lahiri, K.; Raghunathan, A.; Dey, S. Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on , 2000 Page(s): 424 -430
• A new network processor architecture for high-speed communications Xiaoning Nie; Gazsi, L.; Engel, F.; Fettweis, G. Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on , 1999 Page(s): 548 -557

Product Evaluation

• Spider: a high-speed network interconnect Galles, M. IEEE Micro , Volume: 17 Issue: 1 , Jan.-Feb. 1997 Page(s): 34 -39
• Evaluating Network Processors in IP Forwarding Spalink, Karlin, and Peterson, TR-626-00, Princeton University.
• Interfaces to high speed packet buses and switch fabrics JAZiO signal switching technology: a low-cost digital I/O for high-speed applications Haq, E.; Slager, J.; Pecoraro, J.; Johnson, J.D.; Santoro, M.; Tavrow, L.; Wakefield, S.; Weisner, D. IEEE Micro , Volume: 21 Issue: 1 , Jan.-Feb. 2001 Page(s): 72 -81
• A scheduler ASIC for a programmable packet switch Zhang, L.L.; Beacham, B.; Hashemi, M.R.; Chow, P.; Leon-Garcia, A. IEEE Micro , Volume: 20 Issue: 1 , Jan.-Feb. 2000 Page(s): 42 -48

Software aspects of programming processors for networking

• Network processors: a perspective on market requirements, processor architectures and embedded S/W tools; P. Paulin, F. Karim and P. Bromley; Proceedings of the DATE 2001 on Design, automation and test in Europe, 2001, Pages 420 - 429

QoS

• A network processor architecture for flexible QoS control in very high-speed line interfaces Shimonishi, H.; Murase, T. High Performance Switching and Routing, 2001 IEEE Workshop on , 2001 Page(s): 402 -406

Techniques for accelerating network services

• Cache memory design for network processors Tzi-Cker Chiueh; Pradhan, P. High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on , 1999 Page(s): 409 -418
• IP-based design of custom field programmable network processors Bombana, M.; Fominykh, N.; Gorla, G.; Kriajev, A.; Krivosheyin, B.; Rytchagov, J. Electronics, Circuits and Systems, 1998 IEEE International Conference on , Volume: 1 , 1998 Page(s): 467 -471 vol.1

Packet classification

• High-speed policy-based packet forwarding using efficient multi-dimensional range matching; T. V. Lakshman and D. Stiliadis; Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication, 1998, Pages 203 - 214

Router

• Design issues for high-performance active routers Wolf, T.; Turner, J.S. Selected Areas in Communications, IEEE Journal on , Volume: 19 Issue: 3 , March 2001 Page(s): 404 -409
• A delay model and speculative architecture for pipelined routers Peh, L.-S.; Dally, W.J. High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on , 2001 Page(s): 255 -266
• Low-level router design and its impact on supercomputer system performance; V. Puente, J. A. Gregorio, C. Izu, R. Beivide and F. Vallejo; Proceedings of the 1999 international conference on Supercomputing, 1999, Pages 193 - 201
• A 50 Gigabit Per Second IP Router Craig Partridge et al., IEEE/ACM Trans. on Networking, Vol. 6, No. 3, pp. 237-248, June 1998.
• Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers David E. Taylor, Jonathan S. Turner, John W. Lockwood. Washington University in Saint Louis. OpenARCH'01, April 2001.

Novel applications

• Using embedded network processors to implement global memory management in a workstation cluster Coady, Y.; Joon Suan Ong; Feeley, M.J. High Performance Distributed Computing, 1999. Proceedings. The Eighth International Symposium on , 1999 Page(s): 319 -328

Tools / Frame Works

• The Phoenix framework: a practical architecture for programmable networks Putzolu, D.; Bakshi, S.; Yadav, S.; Yavatkar, R. IEEE Communications Magazine , Volume: 38 Issue: 3 , March 2000 Page(s): 160 -165
• INTREPID: an integrated network tool for routing, evaluation of performance, and interactive design Cahn, R.S.; Chang, P.-C.; Kermani, P.; Kershenbaum, A. IEEE Communications Magazine , Volume: 29 Issue: 7 , July 1991 Page(s): 40 -47
• Nectar CAB: a high-speed network processor Menzilcioglu, O.; Schlick, S. Distributed Computing Systems, 1991., 11th International Conference on , 1991 Page(s): 508 -515

Benchmark / Work Load Characteristics

• CommBench-a telecommunications benchmark for network processors Wolf, T.; Franklin, M. Performance Analysis of Systems and Software, 2000. ISPASS. 2000 IEEE International Symposium on , 2000 Page(s): 154 -162
• Characterizing processor architectures for programmable network interfaces; Patrick Crowley, Marc E. Fluczynski, Jean-Loup Baer and Brian N. Bershad; Proceedings of the 2000 international conference on Supercomputing, 2000, Pages 54 - 65
• Investigating QoS support for traffic mixes with the MediaWorm router Ki Hwan Yum; Vaidya, A.; Das, C.R.; Sivasubramaniam, A. High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on , 1999 Page(s): 97 -106

Books