Research Assistants: Y. Song, R. Xu
Sponsor: NSF
The Panorama project, funded by an NSF CAREER Award, investigates the interaction between compiler techniques and architecture designs for the improvement of the memory-system performance on shared-memory multiprocessors. More specifically, it studies both software and hardware methods to shorten the average memory latency and to reduce the memory and network traffic. This research group has engaged in the construction of the Panorama parallelizing Fortran compiler which, in addition to parallelizing DO-loops which contains subroutine calls, uses extensive interprocedural array data flow analysis to better utilize the memory hierarchy in shared-memory multiprocessors (both SMP's and CC-NUMA's.)
In recent experiments, Panorama parallelizes several of the newly-released NASA NPB2.3-serial benchmarks fully automatically within several seconds for each program, and the speedup of the resulting codes on SGI Origin 2000 is shown to be far superior to leading commercial parallelizing compilers. The Panorama compiler is also shown to be capable of parallelizing several important benchmarking programs, such as the Perfect benchmarks, which are known to be extremely difficult. Moreover, it achieves a compilation speed that is ten-times to twenty-times faster than other research prototypes of similar parallelization capabilities, which substantially improves the practical feasibility of interprocedural parallelizing compilers.