Z. Li, J. Huang, and G. Jin. Page Mapping Techniques to Reduce Cache Conflicts on CC-NUMA Multiprocessors. Microprocessors and Microsystems, 22(3-4):165-174, August 1998. Special issue on Parallel Algorithms and Architectures.

S. Cho, J.-Y. Tsai, Y. Song, B. Zheng, S. Schwinn, X. Wang, Q. Zhao, Z. Li, D. J. Lilja, and P.-C. Yew. High-Level Information: An Approach for Integrating Front-End and Back-End Compilers. In Proceedings of International Conference on Parallel Processing, August 1998.

G. Jin, Z. Li, and F. Chen. An Efficient Solution to the Cache Thrashing Problem. IEEE Transaction on Computers, 47(5):527-543, May 1998.

J.-Y. Tsai, Z. Jiang, Z. Li, D. J. Lilja, X. Wang, P.-C. Yew, B. Zheng, S. J. Schwinn, and R. Glamm. Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading. Journal of Information Science and Engineering, 14(1), March 1998. Special issue on Compiler Techniques for High-Performance Computing.

T.N. Nguyen and Z. Li. Interprocedural Analysis for Loop Scheduling and Data Allocation. Parallel Computing, 24(3):477-504, 1998. Special Issue on Languages and Compilers for Parallel Computers.

Z. Li, J. Gu, and G. Lee. Interprocedural Analysis Based on Guarded Array Regions. In Agrawal and Pande, editors, Languages, Compilation Techniques and Run Time Systems for Scalable Parallel Machines, Springer-Verlag, December 1997. Chapter 5.

J. Huang, G. Jin, and Z. Li. Page-mapping Techniques for CC-NUMA Multiprocessors. In Third IEEE International Conference on Algorithms and Architectures for Parallel Processing, pages 91-104, Melbourne, Australia, December 1997.

J. Huang and Z. Li. Reducing Cache Misses for CC-NUMA by Careful Page-mapping. In Tenth International Conference on Parallel and Distributed Computing Systems, pages 417-421, New Orleans, LA, October 1997. International Society for Computers and Their Applications.