Programme

08:00 - 08:30: Breakfast

08:30 - 08:45: Opening Remarks

08:45 - 10:15: Session 1: New Twists on Memory Management

1. •Deconstructing Process Isolation
   

2. Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen Hunt, James Larus (Microsoft Research)
   

3. •Reliability-Aware Data Placement for Partial Memory Protection in Embedded Processors
   

4. Mojtaba Mehrara, Todd Austin (University of Michigan)
   

5. •Smarter Garbage Collection with Simplifiers
   

6. Melissa O'Neill (Harvey Mudd College)
   Warren Burton (Simon Fraser University)
   

10:15 - 10:30: Break

10:30 - 12:00: Session 2: Workload Optimization

1. •Efficient Frequent Pattern Mining on Shared Memory Systems: Implications for Chip Multiprocessor Architectures
   

2. Gregory Buehrer, Srinivasan Parthasarathy, Amol Ghoting (Ohio State University)
   

3. Yen-Kuang Chen, Anthony Nguyen, Daehyun Kim (Intel)
   

4. •Seven at One Stroke: Results from a Cache-Oblivious Paradigm for Scalable Matrix Algorithms
   

5. Michael D. Adams and David S. Wise (Indiana University)
   

6. •Implicit and Explicit Optimizations for Stencil Computations
   

7. Shoaib Kamil (Lawrence Berkeley National Laboratory)
   

8. Kaushik Datta, Samuel Williams (UC Berkeley)
   

9. Leonid Oliker, John Shalf (Lawrence Berkeley National Laboratory)
   

10. Katherine Yelick (UC Berkeley)
    

12:00 - 13:00: Lunch

13:00 - 14:00: Keynote Talk: David Wood (University of Wisconsin, Madison)

1. •Challenges in Chip Multiprocessor Memory Systems
   

14:00 - 14:15: Break

14:15 - 15:45: Session 3: Transactional Memory

1. •What Do High-Level Memory Models Mean for Transactions?
   

2. Dan Grossman (University of Washington)
   Jeremy Manson (Purdue University)
   

3. William Pugh (University of Maryland)
   

4. •Memory Models for Open Nesting
   

5. Kunal Agrawal, Charles Leiserson, Jim Sukha (MIT)
   

6. •Atomicity via Source-to-Source Translation
   

7. Benjamin Hindman, Dan Grossman (University of Washington)
   

15:45 - 16:00: Break

16:00 - 17:00: Session 4: Cache & TLB Design

1. •A Flexible Data to L2 Cache Mapping Approach for Future Multicore Processors
   

2. Lei Jin, Hyunjin Lee, Sangyeun Cho (University of Pittsburgh)
   

3. •A Comprehensive Study of Hardware/Software Approaches to Improve TLB Performance for Java Applications on Embedded Systems
   

4. Jinzhan Peng, Gansha Wu, Guei-Yuan Lueh (Intel)
   

5. Rakvic Ryan (United States Naval Academy)
   

6. Xiaogang Gou (Intel)