Preliminary programme now available

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Call for Participation

MSPC 2006 focuses on improving the memory system performance and correctness of general-purpose programs. MSPC continues the successful series of MSP workshops held in 2002 (Berlin), 2004 (Washington, DC), and 2005 (Chicago). This multi-disciplinary workshop fosters collaboration among researchers in a range of fields including compilers, memory management, programming languages, architecture, operating systems, performance evaluation, and database systems. Papers are solicited on all aspects of memory system performance and correctness. Areas of interest include but are not limited to the following topics:

1. •Analysis of memory systems performance (including power, bandwidth, and latency)
   

2. •Static and dynamic techniques for understanding and improving memory performance
   

3. •Hardware and software techniques for ensuring memory safety and detecting memory-related bugs (e.g., memory leaks, dangling pointers, out-of-bounds memory accesses, invalid C pointer arithmetic)
   

4. •Hardware memory models and their impact on software
   

5. •Specifications of programming language (and library) shared memory semantics
   

6. •Better shared-memory programming models (e.g., transactional memory)
   

7. •Data race detection and debugging of programs with (possibly intentional) data races
   

8. •Managed memory and garbage collection optimizations
   

9. •Memory hierarchy design for chip multiprocessors (CMPs)
   

10. •Pre-fetching and compression to improve memory system performance
    

11. •Code, data, or page placement to eliminate page faults and cache misses
    

12. •Memory system issues in embedded computers and tiny devices
    

13. •Impact of new storage technologies
    

Software, hardware, and hybrid approaches are encouraged.  In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.